1. Field of the Disclosure
This disclosure relates to a liquid crystal display device, and more particularly, to a liquid crystal display device adapted to improve picture quality and a driving method thereof.
2. Description of the Related Art
As the information society spreads, flat display devices capable of displaying information have been widely developed. These flat display devices include liquid crystal display (LCD) devices, organic electro-luminescence display devices, plasma display devices, and field emission display devices. Among the above devices, LCD devices have advantages in that they can be light and small and can implement a low power consumption and a full color scheme. Accordingly, LCD devices have been widely used for mobile phones, navigation systems, portable computers, televisions and so on.
FIG. 1 is a block diagram showing an LCD device of related art, FIG. 2 is a detailed block diagram showing a gate driver in FIG. 1, and FIG. 3 is a circuitry diagram showing a first shift register in FIG. 2.
As shown in FIG. 1, the related art LCD device includes a liquid crystal panel 130, a gate driver 110, a data driver 120, and a timing controller 100. The liquid crystal panel 130 displays the pictures. The gate driver 110 drives the liquid crystal panel 130 by lines. The data driver 120 applies data voltages to the liquid crystal panel 130 by lines. The timing controller 100 controls the gate driver 110 and the data driver 120.
In order to control the gate driver 110 and the data driver 120, the timing controller 100 generates control signals. For example, the timing controller 100 generates a start signal Vst and first to fourth gate clock signals GCLK1 to GCLK4 to control the gate driver 110. The timing controller 100 also generates a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE, a polarity control signal POL, and so on.
The gate driver 110 is directly formed on the liquid crystal panel 130. Such a structure panel is called a Gate-in-Panel. Also, the gate driver 110 includes a plurality of stages ST1 to STn, as shown in FIG. 2. The stages ST1 to STn are connected to one another to form a cascade configuration. Each of the stages ST1 to STn receives an output signal from a previous stage and the three gate clock signals among the first to fourth gate clock signals GCLK1 to GCLK4 which are sequentially applied. The first stage ST1 independently inputs the start signal Vst instead of the previous stage's output signal, because the previous stage did not exist.
Each of the stage ST1 to STn uses the previous stage's output signal and the three gate clock signals of the first to fourth gate clock signals GCLK1 to GCLK4 and generates an output signal Vg1 to Vgn. The output signals Vg1 to Vgn generated in the stages ST1 to STn are applied to gate lines GL1 to GLn on the liquid crystal panel 130, respectively. Such stages ST1 to STn are identical with one another in their internal circuit configuration. Accordingly, for convenience of explanation, the circuit configuration of first stage ST1 will be now described.
Referring to FIG. 3, the fourth gate clock signal GCLK4 and the start signal Vst are applied to the first stage ST1. The first stage ST1 includes a first control portion 112 responsive to the start signal Vst and the fourth gate clock signal GCLK4, controlling a first node Q; a second control portion 114 responsive to the third gate clock signal GCLK3 and the start signal Vst, controlling a second node QB; and an output portion 116 responsive to voltages on the first and second nodes Q and QB, selectively outputting the first gate clock signal GCLK1 and a first supply voltage VSS.
The fourth gate clock signal GCLK4 turns on a second transistor T2 so that the start signal Vst is charged into the first node Q through a first transistor T1 and the second transistor T2, during a first interval. Then, a sixth transistor T6 is slowly turned on by the voltage on the first node Q. A fifth transistor T5 is also turned on so that the first supply voltage VSS is charged to the second node QB. The voltage VSS on the second node QB turns off third and seventh transistors T3 and T7. Accordingly, although the sixth transistor T6 is slowly turned on, the first gate line GL1 maintains a low level state due to the first gate clock signal GCLK1 of low level, during the first interval.
For a second interval, the start signal Vst and the first to fourth gate clock signal GCLK1 to GCLK4 are not applied. The status of the first stage ST1 in the first interval continues even-in spite of for the second interval.
The first gate clock signal GCLK1 is applied to a source terminal of the sixth transistor T6 during a third interval. Then, a bootstrapping phenomenon is caused by an internal capacitor (or a parasitic capacitor) Cgs between the source and gate terminals of the sixth transistor T6, thereby increasing the voltage on the first node Q connected with the gate terminal of the sixth transistor T6. As a result, the sixth transistor T6 is fully or completely turned on so that the first gate clock signal GCLK1 of high level is charged on the first gate line GL1 of the liquid crystal panel 130 via the sixth transistor T6.
For a fourth interval, a second supply voltage VDD is charged to the second node QB through a fourth transistor T4 which is turned on by the third gate clock signal GCLK3. At this time, since the first gate clock signal GCLK1 has the low level, the bootstrapping phenomenon ceases so that the first node Q maintains the previous voltage, i.e., the voltage of the start signal Vst. The voltage on the second node QB turns on the third and seventh transistors T3 and T7, thereby charging the first supply voltage VSS to both of the first node Q and the first gate line GL1 of the liquid crystal panel 130 through each of the third and seventh transistors T3 and T7.
In this manner, the start signal Vst and the first to fourth gate clock signals GCLK1 to GCLK4 should be applied from the timing controller 100 in order to drive the gate driver 110.
However, when the first gate clock signal GCLK1 is compared with the second to fourth gate clock signals GCLK1 to GCLK4 in the high level interval, the first gate clock signal GCLK1 has a relatively short high level interval, as shown in FIG. 4. Accordingly, thin film transistors on the first gate line GL1 each have a relatively short turning-on interval in comparison with those on the other gate lines GL2 to GLn of the liquid crystal panel 130, thereby allowing pixels on the first gate line GL1 to be brighter than those on the other gate lines GL2 to GLn.
As a result, a brightness difference between the pixels of the first gate line GL1 and the pixels of the other gate lines GL2 to GLn is generated, thereby deteriorating the quality of picture.